1. Field of the Invention
This invention relates in general to a memory and specifically to writing back values read from a memory cell.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a portion of a memory 101. In the example shown, memory 101 is a static random access memory (SRAM). An SRAM memory includes an array of volatile SRAM memory cells for storing data. The SRAM cells of memory 101 (with cells 103 and 105 shown in FIG. 1) are arranged in rows and columns. In one example, the cells of each column are coupled to a pair of bit lines (BLB and BL) that are used for reading and writing data in the cells of the column. The bit lines are connected to a sense amplifier 110 that is used to sense a voltage differential on the bit lines during a read cycle and amplifies the difference to provide an output based on the differential to determine a value stored in a memory cell. Sense amplifier 110 receives a sense enable signal (SE) for enabling the sense amplifier during a read operation and a sense amplifier precharge signal (SAPC) for precharging bit lines SAB and SA of the sense amplifier to an operating voltage level (VDD). In the example shown, sense amplifier 110 includes inverters 143 and 145.
In the example shown, cell 103 is a 6 transistor SRAM cell that includes access transistors 107 and 109 for coupling the memory cell data latch to the bit lines BLB and BL. The access transistors are controlled by a word line (e.g. WL1) and are made conductive when data is to be read or written to the cell. Each word line is coupled to access transistors of other cells located in the same row (not shown). In the example shown, the latch of cell 103 includes cross coupled transistors 111, 113, 115, and 117. Transistors 111 and 113 are P-channel transistors and transistors 115 and 117 are N-channel transistors. Each latch circuit includes two data storage nodes 119 and 121 which are designed to be biased at opposite complementary voltage states for storing data.
As the memory operating voltage (VDD in the diagram) is reduced, the operating voltage approaches the threshold voltages of the latch. Accordingly, the N-channel transistor (115 or 117) may not be fully conductive to hold a low voltage state (e.g. 0V) at storage node 119 or 121. If the one node is not held to the low voltage state, then the P-Channel transistor (111 or 113) may not be fully conductive to hold the other data storage node at the high voltage state.
These voltage problems are exacerbated during a read of the memory cell. For example, during a read of cell 103 when node 121 is at a low voltage state and node 119 is at a complementary high voltage state, the assertion of the word line signal causes transistor 109 to be conductive which pulls up slightly the low voltage at node 121 which may be referred to as read disturb. This causes the conductivity of transistor 111 to become weaker and increases the conductivity of transistor 115, thereby lowering the voltage of node 119. Lowering the voltage of node 119 reduces the conductivity of transistor 117 and increases the conductivity of transistor 113, thereby raising the voltage of node 121 further. For circuits where the memory operating voltage has been lowered, a lowering of the voltage at node 119 from the high voltage state due to the assertion of the word line, may cause transistor 117 to become non conductive to where node 121 switches voltage states. This may be referred to as read failure for an SRAM memory where reading the memory cell flips the state of the memory cell. Accordingly, reading an SRAM memory cell at a low operating voltage may cause the contents of the cell to become unreliable during a memory read.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.